Northrop Grumman Sr. Principal ASIC DFT Engineer in Linthicum, Maryland
At the heart of Defining Possible is our commitment to missions. In rapidly changing global security environments, Northrop Grumman brings informed insights and software-secure technology to enable strategic planning. We're looking for innovators who can help us keep building on our wide portfolio of secure, affordable, integrated, and multi-domain systems and technologies that fuel those missions. By joining in our shared mission, we'll support yours of expanding your personal network and developing skills, whether you are new to the field or an industry thought-leader. At Northrop Grumman, you'll have the resources, support, and team to do some of the best work of your career.
Northrop Grumman Mission Systems (NGMS) is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse individuals in Digital Technology. Qualified applicant will become part of the Digital Technology and Secure Processing department, which specializes in product designs for a variety of applications from undersea to outer space.
Roles and Responsibilities:
The individual will be responsible for DFT (Design for Test) aspects of ASIC Design. Successful candidates will have a thorough understanding of digital design concepts and have prior experience with ASIC development process. Must be knowledgeable in VHDL or Verilog RTL coding and be highly proficient in DFT methodologies.
This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.
Bachelor's degree in Electrical Engineering or a related discipline and a minimum of 9 years of relevant experience (7+ years with an MS)
Experience in full product life cycle of ASIC Design
Experience with Cadence, Mentor and/or Synopsys test insertion and ATPG tools
Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, and test compression
Experience with at-speed scan testing
Experience integrating DFT features of 3rd party IP
Experience with JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)
Experience with memory BIST and logic BIST
Experience generating test patterns and analyzing and debugging test failures
Experience working with test engineers to implement ATPG vectors on tester hardware
Proficiency in HDL (VHDL/Verilog)
Proficiency in scripting languages such as Tcl, Python or Perl
Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
U.S. citizenship with the ability to obtain and maintain a Secret security clearance
Effective communication and presentation skills and high proficiency in technical problem solving
Master's Degree in Electrical or Computer Engineering
Active DOD Secret Clearance or higher
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.
Job Category : Engineering